A digital system-on-chip in a 1.2 V 100 nm process has 200 million transistors, of which 20 million are in logic gates and the remainder in memory arrays. The average logic transistor width is 12 and the average memory transistor width is 4. The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage is 20 nA/um for low-threshold devices and 0.02 nA/um for high-threshold devices. Gate leakage is 3 nA/um for thin oxides and 0.002 nA/um for thick oxides. Memory uses low-