Semiconductor Engineering

UVM Register Layer: The Structure

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full ...
Design-Reuse

Unveiling Efficient UVM Register Modeling with IDesignSpec™ GDI by Agnisys®

In the field of semiconductor design and verification, the Universal Verification Methodology (UVM) is a key tool for achieving robust and efficient verification environments. At the heart of UVM lies ...
Design-Reuse

Using UVM Register Model

When I was preparing for a customer presentation on UVM RAL, I could not understand what the UVM base class library is saying about updating the values of desired value and the mirror value registers.
Business Wire

Agnisys Offers Free Register Generator for UVM

SAN JOSE, Calif.--(BUSINESS WIRE)--Agnisys today announced a free version of its Hardware Specification tool – IDesignSpec™. It enables users to capture hardware specification that is automatically ...
Semiconductor Engineering

Beyond UVM Registers — Better, Faster, Smarter

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register ...